Reuse of test generation methods for embedded systems

In this paper test generation methods and appropriate fault models for testing and analysis of embedded systems described as (extended) finite state machines ((E)FSMs) are presented. Compared to simple FSMs, EFSMs specify not only the control flow but also the data flow. Thus, we define a two-level fault model to cover both aspects. The goal of this paper is to reuse well-known FSM-based test generation methods for automation of embedded system testing. These methods have been widely used in testing and validation of protocols and communicating systems. Dependability is one of the most required properties of safety-critical embedded systems because this property relates to avoidance of faults: fault prevention, fault tolerance, fault removal and fault forecasting. This has, however, an implication that development of such systems is usually error-prone and very costly task. One means to attain this property and reduce the development cost is the introducing of formal methods. Indeed, these substantially contribute in the automation of many tasks of the development cycle and allow an unambiguous system specification and testing. In particular, (E)FSMs-based specification and testing is more advantageous because (E)FSMs support the formal semantic of already standardised formal description techniques (FDTs) despite of their popularity in the design of hardware and software systems. In addition, FDTs allow a user-friendly description of complex specifications by attaching single ‘E’FSMs to each other in an hierarchical structure. Keywords Embedded systems, formal specification, testing and validation, state/transition-based models, formal description techniques



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